China Campus-Digital Design Engineer for IP Development

Location: Wuhan,China

As part of the Solutions Group at our Wuhan Design Center, China, the selected candidate would be working on one or more aspects of the development of DesignWare family of synthesizable cores, including Specification, Architecting, Design, Verification and Release engineering for Synopsys IP products. The domains would span across areas such as DDR,AMBA (AHB, AXI)/USB3, Gigabit Ethernet, Multimedia Cards, and MIPI.

    

Post the orientation and training, the candidate would be assigned to work on either the design or verification tasks based on aptitude and business needs; the candidate will be part of a global team of expert Design/Verification Engineers.

  

On the design side, the candidate would work on System level and RTL based hardware design using HDLs such as Verilog, and System Verilog;

will use Lint tools for rule checking, Synthesis tools, and timing analysis; the designs may involve use of low power design techniques and implemented using Unified Power Flow.

  

On the verification side, candidate would work on latest verification methodologies such as UVM, VMM.

The verification tasks would include building or enhancement of CRV based complex test environment, test case writing in OOPS based languages such as SystemVerilog, running tests and debugging failures;

will include Functional coverage implementation and would involve usage of industry standard simulators such as VCS.

  

It is essential that the individual has –

        

The position offers lot of learning opportunities for the candidate by working with the #1 Interface and wide portfolio of IP Provider in the Industry.