2019 Synopsys China Internship Program
Location： Shanghai/ Wuhan
Available Projects：
- Timing Analysis Automation for ASIC Backend Design
- Integrated Testing Environment Development
- Simulation Window for Dynamic Timing Analysis and Validation
- Synthesizer Feature Development on Emulation Tool
- White Box Test for Graph Theory - Algorithm Research
- Compiler Enhancement for VCS (Verilog compiler) Incremental
- Machine Learning applying on Physical Synthesis tool
- More……
要求：
l 在校研究生或本科生，在读计算机工程、软件工程、电子\通讯等或相关专业
l 具备敏捷的学习能力，较强的技术分析和解决问题的能力
l 有一定的技术描述和表达能力，善于和团队交流和相互学习，
l 具备以下任何一项或多项技能：
- 熟悉在 Unix/Linux 平台且有C++ programming的经验
- 或，熟悉脚本语言Python, Shell, TCL，或一定运用实践经验等
- 或，了解建模、大数据处理、图论、算法、机器学习基本知识或相关实践经验
- 或， 熟悉Verilog HD 或有 programming 的经验
- 或，熟悉ASIC前端/后端设计流程 和 基本验证方法论
Requirements：
l Currently on Master and PhD study, the major is in Computer engineering, Computer Science/Software engineering or Electronic / Telecommunication Engineering or relevance
l Agile learning capability, Good analysis and Problemsolving skills
l Can explicitly present technical issues and can be willing to communicate and interact with people in the team
l Be skillful in one or more of the following fields:
- C++ programming development experience on Unix/Linux
- Or, Script experience via Python, Shell or TCL, etc.
- Or, Basic knowledge of modeling, big data, graph theory, algorithms and machine Learning
- Or, have the programing experiences or knowledge on Verilog HDL
- Or, Basic knowledge of ASIC Frontend/Backend design flow &verification methodology